Design Verification Engineer Intern

.Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com .

Join Astera Lab’s ASIC team as Design Verification Co-Op working on the forefront of high-performance compute and networking standards in advanced CMOS process nodes. The ideal candidate will be passionate about silicon engineering with a background in VLSI and/or computer architecture. In this position you will be responsible for design and/or verification of blocks using leading edge methodology and tools.

Basic qualifications

• Completed 3 rd year of study, minimum GPA: 3.5
• Strong academics and technical background in either Computer Engineering or Electrical/Electronic Engineering.
• Authorized to work in Canada and start immediately.

Required experience

• Courses/Projects in digital logic, programming languages, computer architecture.
• Hands-on and knowledge of RTL design languages and tools including Verilog, System Verilog.
• Familiarity with any of the scripting languages Python, Perl, etc. and hands-on experience in C/C++.
• Detailed oriented with strong analytics and debugging skills.

Preferred experience

• Knowledge of high-speed interfaces like PCIe, DDR, HBM, Serdes.
• Knowledge of communication interfaces like SPI, I2C, JTAG.
• Courses in digital communications and computer networks.
• System Verilog test bench(UVM)
• Familiarity with Synopsys EDA tools.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.